PCIe Protocol Analyzer di Sitiawan

Key features

• PCIe Gen1/2/3/4/5-X4/8 Protocol Decode and Analysis.
• Currently supports four/eight lane PCIeGen1/2/3/4/5 Bus.
• M2/U.2/CEM/E1.S/SD Express interposer for speeds up to PCIe Gen5 is standard offering with protocol analyzer.
• NVME Protocol Decode Capabilities
• Optional solder down probe tips for four lanes for speeds up to PCIe Gen3 (8Gbps)
• Protocol Decoding of TS1, TS2, TLP, DLLP Packets.
• Hardware based protocol packet (TS1, TS2 and IDLE) filter capabilities.
• Software based search, filter-in and filter-out capabilities.
• Hardware based protocol aware trigger capabilities based on TS1, TS2, TLP and DLLP packet contents.
• Advanced multi-level if-then-else if trigger capabilities.
• Standard buffer size of 16GB and expandable to 64GB combined for TX and RX.
• Detailed view of each TLP/DLLP with all field values.
• LTSSM Analysis for PCIe protocol traffic.
• Memory segmentation with each segment with different trigger condition
• Trigger out signal at trigger event allows the triggering of other instruments such as an oscilloscope.
• Interface to host system using USB 3.0.
• Decoded data packets can be exported to .txt file for further analysis.
• PGY Protocol Analyzer is light weight and can be deployed for on-site/ field tests.
• Field upgradeable to enable easy maintenance and remote firmware upgrade to latest feature set.